In forming damascene structures in integrated circuit manufacturing processes, barrier layer uniformity is critical for achieving acceptable copper diffusion resistance and for achieving electrical resistances within required IC performance standard constraints. A damascene opening, for example a dual damascene opening is formed in an inter-metal dielectric insulating layer by a series of photolithographic patterning and etching processes, followed by formation of a barrier layer and a metal filling process.
Increasingly, low-K layers are required to reduce signal delay and power loss effects as integrated circuit devices are scaled down. One way this has been accomplished has been to introduce porosity or dopants into the dielectric insulating layer, also referred to as an inter-metal dielectric (IMD) layer.
One problem with using porous low-k materials together with using copper as the metal filling in a copper damascene process is the susceptibility of the low-k materials to copper diffusion into the IMD layers, which has the effect of altering the dielectric constant of the IMD layer and degrading damascene electrical resistivity. Prior art processes have proposed different barrier layer materials for use with copper and porous low-k materials including refractory metals and refractory metal nitrides have been used to both form a robust barrier layer while achieving reduced copper damascene electrical resistivities.
As device characteristic dimensions have decreased below about 0.25 microns and lower including less than about 0.17 microns, adequate step coverage of damascene openings with barrier layer deposition methods has become a challenge. Prior art processes have attempted to use various physical vapor deposition (PVD) processes to achieve adequate step coverage. However, PVD processes are inherently limited in depositing thin layers of materials in smaller openings due to the physical nature of sputter deposition processes. For example, PVD processes tend to form a higher coverage at the bottom of the opening compared with the sidewall portions. In addition, with respect to a dual damascene process, barrier layer coverage tends to be thinned at corner portions, e.g., bottom via corner and via/trench transition portions of the dual damascene, making copper diffusion into the IMD layer more likely. In addition, barrier layer coverage over the via bottom portion and sidewall portions in the upper trench portion is generally formed with a relatively increased thickness thereby undesirably increasing electrical resistances.
There is therefore a need in the semiconductor processing art for a method for forming copper damascenes with improved barrier layer coverage uniformity while reducing a contribution to electrical resistivity thereby improving performance and reliability of an integrated circuit.
It is therefore among the objects of the present invention to provide a method for forming copper damascenes with improved barrier layer coverage uniformity while reducing a contribution to electrical resistivity thereby improving performance and reliability of an integrated circuit, in addition to overcoming other shortcomings of the prior art.